资源列表
simulation_of_blocking_rate
- 无线通信中阻塞率的仿真，排队论相干理论讲解-Blocking rate in wireless communications simulation, queuing theory coherent theory to explain! ! ! !
cordic_generic
- 本人根据opencores.org上的cordic算法改写的可配置位宽的cordic算法，并且在原始的级联型的基础上编写的循环(iterative)型的cordic,可通过generic配置。带一个不可综合和可综合的testbench(for altera)。稍微改动可应用于xilinx fpga-a generic synthesizable cordic with 2 modes: cascade and iterative. based on opencores.org version,
VHDL_TipsTricks
- 一个FIR的vhdl基本设计介绍，优化。代码与图文相互对应，简单易懂-introduction to VHDL design with codes related to optimized circuit.
RAM
- 用VerilogHDL写的ram程序，对初学者会有帮助。-Writing the ram with VerilogHDL procedures will be helpful for beginners.
connect20090223
- fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
watch
- 运用VHDL语言编写的秒表程序，能够精确的计时-failed to translate
VHDL100li
- VHDL 100例,描述VHDL的重要应用,实用的例子.-VHDL 100 cases, important applications of VHDL descr iption, practical examples.
VGA_interface_with_FPGA
- 对于设计VGA接口非常有帮助，无需专门的VGA芯片，设计实现方便-VGA interface for the design of very helpful, without specialized VGA chip, designed to facilitate implementation
verilogsram
- Verilog语言对SRAM的操作,也提一些简单的快速操作SRAM的技巧。 -Verilog language to the SRAM operation, also raises simply some operates SRAM fast the skill.
337531448051UART
- this UART reference
rd1042_source_code
- hi this reference code for UART use UAER0_3-hi this is reference code for UART use UAER0_3