- snmp__3.2 snmp++3.2是HP公司基于snmp协议的开发包
- white-noise 应用matlab生成白噪声和有色噪声的程序设计
- BPSK_BER This file is simulation file for digital communication system.
- Wireless_LAN_without_pilot This matlab simulation source code for ASP digital communication system.
- ListViewPagingSimple Android ListVisw实现异步加载图片
- WindowsAPI Windows API函数
资源列表
dianzizhong
- 电子时钟程序设计与仿真验证，VHDL语言-Clock Electronics Design and Simulation, VHDL language
Virtex-5family
- Virtex™ -5 系列提供 FPGA 市场中最新最强大的功能。Virtex-5 系列采用第二代 ASMBL™ （高级硅片组合模块）列式架构， 包含四种截然不同的平台（子系列），比此前任何 FPGA 系列提供的选择范围都大。每种平台都包含不同的功能配比，以满 足诸多高级逻辑设计的需求。-Virtex ™ -5 family provides the latest FPGA market, the most powerful features. Virtex-5 s
pinlvji
- 频率计程序设计与仿真验证，基于VHDL语言-Cymometer process design and simulation verification, based on the VHDL language
jisuanqi
- 用VHDL语言实现通用计算器设计，MUXPLUS2软件仿真验证-Implementation using VHDL language design generic calculator, MUXPLUS2 software simulation to verify
jiaotongdeng
- 交通灯控制系统VHDL源码，用VHDL语言、MAXPLUS2环境设计实现-VHDL core
200632610274783742
- 常用VHDL程序，包括27个程序，详情见附件 ，详情见附件-VHDL common procedures, including 27 procedures, as detailed in attachment, as detailed in attachment, as detailed in annex
i2c.tar
- 是个I2C软核，使用verilog和vhdl实现的，含有testbench。-this is soft core of I2C in verilog rtl and VHDL.
adder
- 用VHDL语言实现半加器。已经通过编译和仿真-Implementation using VHDL language half adder. Has passed the compiler and simulation
ls138
- 用原理图的方式编程实现74ls138模块功能，已经通过编译-Schematic way by programming 74ls138 module implementation has passed the compiler
t1
- 带清零和重置功能的十进制计数器，可以用LED灯显示结果-Cleared and reset with the decimal counter, can use LED lights display the results
PLD_SRAM
- PLD自增读写SRAM,有好的参照作用，希望大家指点和帮助。-PLD by reading and writing since the SRAM, has reference to the role of good, I hope everyone pointing and help.