资源列表
mux
- verilog code it is about multiplexer
serial
- 此为Verilog写的功能测试函数，主要用于模块的测试，本程序已调试成功。-This is the function of test functions written in Verilog, mainly used in the test module, the program has been successful debugging.
vedio_format
- 本代码是bt1120 格式产生以及转换为rgb源代码，开发环境为vhdl。-this code describe the bt1120 generator and change form soure code.
VD_212_correction
- 对田耘等所著《无线通信FPGA设计》中第324页代码错误进行了更正，并对代码进行了注释。同时给出了测试激励文件。-Tian Yun and other book Wireless Communications FPGA design on page 324 of the code error has been corrected, and the code of the comments.At the same time gives the test bench files.
fenpin5_5
- Verilog 语言实现利用FPGA对输入方波实现5.5分频-the frequency of a rectangular wave is divided 5.5 using the FPGA
master_bla
- master bla altera quartus II version 15
altdq_dqs2
- altera ip a ltera ip-altera ip altera ip altera ip
alt_xaui
- altera ip a ltera ip-altera ip altera ip altera ip
DTSM
- 在开发板上可以实现从00到59的计数，相当于一个60进制的计数器，里面包括了将脉冲分频的代码编写-In the development board can be achieved 00 to 59 counts, the equivalent of a 60 hexadecimal counter, which includes the pulse frequency of the code
descore_latest.tar
- VHDL implementation of the classic DES block cipher (interactive architecture)
pwm_latest.tar
- pulse width modulator, work as one PWM or one timer. 16 bit main counter
scalable_arbiter_latest.tar
- a scalable synchronous round-robin arbiter. The arbiter is designed to run at reasonable clock speed with up to hundreds of request lines, and it grants in just a few clock cycles.