资源列表
chuzuche
- 出租车计费系统，我的课程设计。希望大家多多指点-Taxi billing system, I designed the curriculum. I hope everyone a lot of advice! !
3to8decoder
- 3 to 8 decoder is used to decode from 3 bit data to 8 bit data used in many applications
KD_CPU_src
- verilog语言写的8位CPU源代码，基本的算术运算和逻辑运算，对于学习计算机原理和verilog语言都有良好的效果-Verilog Language Writing 8-bit CPU source code, the basic arithmetic operations and logic operations, the study of computer principles and Verilog language has good results
barrel_shifter
- VHDL实现的桶型移位器，能在一个时钟周期实现对数据的（0－12位）算术右移-VHDL implementation of a barrel—shifter, able to achieve at one clock cycle of data (0-12 bit) Arithmetic Shift Right
nios_small
- Nios II最小实验系统，适合Nios II的初学者进行试验使用。-The smallest example for Nios II
clktest
- 在开发过程中，通常要进行时钟可靠性测试，主要有相位的变化 、占空比的变化。本代码实现了时钟相位变化和占空比的变化。-In the development process, usually the reliability of the test clock, there are phase changes, the duty cycle changes. Implementation of the code phase of the clock change and the duty cycle
FPGA_Code_and_training_materials
- 压缩包内包含了：FPGA设计初级班和提高班培训课堂PPT；实验的源代码；实验指导书！-Compressed packet contains: FPGA design of the primary classes and training classes improve classroom PPT experiment' s source code experimental guide book!
2008.09-scripts_only
- synopsys icc 使用参考脚本-reference scr ipt of synopsys icc
lcdfinal
- LCD显示，用verilog写的，quartus-LCD display，verilog，quartusII
KX_7Cprogramstatement
- 杭州康芯的FPGA实验板的编程使用说明，ppt格式图片实例说明-KX-7C statement of FPGA lab
FPGAPLLdesign
- 基于FPGA和PLL的函数信号发生器时钟部分的实现-FPGA+PLLdesign and practice
lcd_demo
- 一种基于FPGA和quartusII技术开发的彩色LED显示测试程序-colored LED