资源列表
FPGA-LCD1602
- 基于FPGA的LCD1602显示，可根据实际内容修改显示内容-FPGA-based LCD1602 display can be modified according to the actual contents of display content
XC4VLX40_FGPA
- 使用xinlinx的XC4VLX40_FGPA编写的串口程序-XC4VLX40_FGPA of xinlinx, the seiral communication program
dffasynchronous
- this ram both asynchronous and synchronous reset signals which is basic for any registers and basic memory element-this is ram both asynchronous and synchronous reset signals which is basic for any registers and basic memory element
ram
- a 16 by 4 ram is used for many applications as a basic component such as fifo and stack etc
simudata_generater
- itu656视频模拟源 可以在fpga设计中验证你的系统 丢不丢数据 zhichiyixia-Analog sources can be ITU656 Videos FPGA design verification at the system you lose do not lose data zhichiyixia
Electronic_combination_lock
- 实现电子密码锁的功能，有密码出错，修改密码等功能-Electronic combination lock
DES_IP
- 有效的改进3-DES算法的执行速度，采用了多级流水线技术，设计了一种高速的硬件结构，使得原来需要48个时钟周期才能完成的运算，现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中，大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed
waveformgeneratorincludetestbench
- 用VHDL语言编写的波形发生器（含test beach）-Using VHDL language waveform generator (including the test beach)
pinlvjin
- 基于FPGA的频率计模块设计，带quartus下的图形文件-FPGA-based modular design of the frequency meter with graphics files under Quartus
FPGA_7279
- 基于FPGA的7279键盘数码管驱动，硬件实测，完美运行-FPGA-based digital control of the 7279 keyboard-driven, hardware measurement, perfect run
par_fir
- FIR滤波器流水线结构代码，通过流水线结构与分布式算法的结合-Pipelined FIR filter structure code
MedFilter_VHDL
- 用VHDL实现了Matlab中MedFilt1函数3阶中值滤波。进行排序时没有用软件使用的排序法，而是通过简单的比较实现。-VHDL implementation using the Matlab function MedFilt1 of 3-order median filter. Sort of no use when the software used to sort the Law, but through a simple comparison of implementation.