资源列表
project5_UART
- It is UART protocol in VHDL. it has two files. one is transmitter and one is receiver.
non--restoring
- it is dividing non restoring algorithm implementation using verilog language.
da_80m_10m
- AD9747测试Verilog测试程序,FPGA为xilinx的SP6-the test program of AD9747，FPGA IS SP6
uartverilog
- 用verilog编写的串口通信程序，真的很不错，推荐给大家一起学习一下。希望能有所帮助。-With verilog prepared by the serial communication program, really good, recommend it to everyone learning together about. Hoping to help.
i2c_master
- I2C master 16 bit addr verlog 代码-verlog i2c master
i2c_slave
- I2c slave 16 bit data verilog 代码-i2c slave verilog code
LAB7_1
- LAB 7 VERILOG DE2-115
LAB7_3
- lab7 part 3 verilog de2-115
async.v
- verilog code for UART module
SIN_GNT
- LPM_ROM定制。简单的正弦波发生器。 Verilog HDL语言设计。 EP4CE15F17C18N实测可用。-LPM_ROM customization. Simple sine wave generator. Verilog HDL designs. EP4CE15F17C18N measurement available.
Verilog.HDL
- <精通Verilog.HDL语言编程_源码>-< Proficient Verilog.HDL source programming language _>
LCD1602
- 液晶1602的FPGA驱动程序，可实现16x2的字符显示-1602 FPGA LCD drivers, enabling 16x2 character display