资源列表
d02
- 此程序为脉宽测量电路vhdl代码，能够对输入的脉冲信号用10HZ时钟进行计数，输出计数结果。主模块调用显示、计数、控制三个模块实现主体功能
AES_enc_core_tb
- this code discribers testbench for aes algorithm. it is written by .vhdl
OPERATION_UNIT
- 本程序为加密芯片内部加密运算单元部分，包括32位减法器、移位寄存器、加/减法器、寄存器等，对密码芯片运算部分设计具有一定指导意义-The procedure for encryption chip unit internal encryption algorithms, including 32-bit subtraction, and shift register, add/subtraction, and register and so on password-chip design has
ic6821_latest.tar
- vhdl core of IC6821 code
m_ds1620_ctrl
- 完成对温度控制芯片ds1620的温度控制，使用verilog实现-Complete the temperature control chip DS1620 temperature control, the use of Verilog to achieve
multi8x8
- 节约资源型 8位*8位 运算VHDL代码，采用串行运算，8 个时钟周期完成一次运算。QUARTUS下已验证-resource conservation-8 * 8 Operational VHDL code, using serial computation. 8 clock cycles to complete an operation. QUARTUS has been under test
iic_com
- iic代码verilog，如果有什么特别的问题，请加593283938，详细交流-iic verilog
clk
- 五分频时钟的产生,分为两个，一个是不带边缘检测，另外一个带边缘检测-Fifth generation of the clock frequency is divided into two, one is a non-edge detection, and the other with edge detection
ebiu_ctl
- VHDL语言编写的外总线控制器，带有aes加密模块-VHDL language external bus controller, with aes encryption module
idt71v416s10
- code for ram in verilog hdl
Meter-VHDL-code
- 基于FPGA的计价器系统 FPGA；VHDL语言；出租车计价器-The Meter Design Based on FPGA FPGA VHDL Language Taxi meter
cs5533
- spi读写CS5533程序，已经调试过，用于仪器中，方便使用-spi write CS5533 program is debugged, for the instrument, easy to use