资源列表
clock
- 一款多用电子时钟设计源程序 本源程序系`一款多用电子钟芯片 源程序,可有3开3关定时,且有受双限触发的定时口 该程序硬件系采用PIC16C55芯片LP振荡方式外接32768Hz晶振
dds_vhdl
- 用VHDL实现的DDS逻辑，大家可以参考下
lift
- 采用vhdl语言的电梯控制器源代码，能够实现报警，等待，并采用了标准的最优电梯运动路线。
Sum_of_2_rand
- We produce two 5-bit random numbers and then adds them. The two random numbers are generated by pressing two different push-buttons on the lab board. The addition is controlled by a third button, button3. it can be implemented on the Atlys board.
I2C_WRITE
- Verilog编写iic总线代码 控制EEPROM的写程序-Verilog code written iic bus EEPROM write control procedures
LFSR
- LFSR模块，单个模块，实现移位寄存器，生成测试用pattern-LFSR
ram
- 基于FPGA的rom程序（verilog）-rom procedure
Unsigned-MultiplicationBooth
- 基于booth算法的移位操作，对带符号数进行乘法运算。-Shifting operation based on the booth algorithm, and the number of unsigned multiplication.
yuandaima
- FPGA多功能数字钟，描述语言VHDL，软件环境QuartusⅡ-FPGA multi-function digital clock, descr iption language VHDL, Quartus Ⅱ software environment
timers.pspice
- PSpice model for 555 timer
expi
- Vhdl实现计算exp功能 在apex20k上经过验证-Vhdl achieve in terms exp function on proven apex20k
bit_synchronize
- 位同步例程源代码,FPGA应用领域，Verilog-Bit synchronization routines source code, FPGA applications, Verilog