资源列表
vhdl2
- 2 programs of basic gates.
ftdd
- 在fpga中实现demosaicing的功能-Implemented in fpga function demosaicing
jnsn
- vhdlcode for a johnson counter-vhdlcode for a johnson counter
de_ct
- dual Elevator code devoleped for FPGA
jiafaqi
- 使用硬件描述语言设计的加法器，现代逻辑器件-Hardware descr iption language design adder, modern logic devices
image_combine_v
- 用于在FPGA中实现图像叠加字幕，字符为FPGA内部rom存储的点阵。-combine word on video stream in FPGA
4
- VHDL CODE FOR stepper motor control
yibufifo
- 基于verilog的异步驱动电路的设计传输实现与研究详解-Verilog-based asynchronous driver circuit design to achieve transfer and research Detailed
uart
- 串口的收发程序，可修改波特率，还有LED显示数据的收发-Serial port to send and receive procedures, can modify the baud rate, and the LED display data transceiver
FIFO
- 用verilog实现异步FIFO，代码中有两个模块，使用时注意顶层模块和底层模块，用quartus2即可打开直接使用。-Verilog using Asynchronous FIFO, the code has two modules, when the attention of top-level module and the bottom module, with direct access to open quartus2.
shuzidianzizhong
- 基于VHDL 数字电子钟设计（时、分、秒），有校时，分频，倒计时流水灯灯功能。-Based on VHDL VHDL-based design of digital electronic clock (hours, minutes, seconds), there is the school, the frequency, the countdown water lights lamp function.
common-mul
- 常用乘法器设计,有详细的步骤-Common multiplier design；