资源列表
VGA2
- VGA controller initialy designed for altera DE2 FPGA with 10 bits DAC. probably works with other systems if you have the correct clock source.
m_seq
- 用VHDL代码编写的m序列发生器，包含发生器和测试用例模块-M sequence generator written in VHDL code, including the generator and the test case module
rs232
- verilog HDL FPGA串口接受与传输,用于其他电子设备与FPGA之间通过串口进行数据传输-the verilog HDL FPGA serial port receive and transmission, data transmission through the serial port for other electronic equipment and FPGA
MII_RxMAC
- Ethernet MAC-MII interface of Receive
VERILOG-CAR-TEST
- 基于FPGA的Verilog语言的智能小车，已经经过测试。-FPGA-based smart car Verilog language, and has been tested.
FIFO_2
- VERILOG Synchronous FIFO. 4 x 16 bit words.-VERILOGSynchronous FIFO. 4 x 16 bit words.
Qpsk_sin
- Program to generate a QPSK wave.
FSK-decoding
- 应用 VHDL 对 FSK 实行译码仿真实现,效果理想-FSK decoding
dwn_sampler
- Multirate digital signal processing system which includes sampling rate conversion. This technique is necessary for systems with different input and output sampling rates, as the proposed multirate device is downsampler FPGA implementation of
clock_top2
- 数字钟的vhd文档，个人感觉还是蛮完善的，大家可以下载了一同改进。-figures minute vhd files, individuals still feel pretty good, we can improve downloaded together.
chengxu
- 实现用PG12864LCD设计的指针式电子钟-Realize PG12864LCD pointer type design with the electric clock
run_led
- verilog顺序操作实现三个LED灯轮流闪烁，产生流程等的效果。-verilog sequential operations to achieve three LED lights flashing alternately, processes, etc. to produce results.