资源列表
Divider
- VHDL代码实现分频器设计 分频器系统时钟20万分频 上升沿触发-VHDL code Divider Design The system clock frequency divider 20 extremely Rising edge triggered
1000hz
- 产生相应的标准的上升沿触发信号，并且有2倍频功能-The rising edge of the corresponding standard generated trigger signal, and features a 2 octave
RAM
- Nios ii双口ram,用于MCU通过nios ii进行双口ram通信,verilog格式.-Nios II dual port RAM, for MCU dual port RAM communication, through the Nios II Verilog format.
statemachine
- An example of state machines
switch-control-LED
- 是单片机学习的入门的必学经典程序，适合初学者理解和学习。-The introduction of the single chip microcomputer is learning will learn classic procedures, is suitable for beginners to understand and study
shizhongpaobiao
- 一个识字跑表可以做秒表使用有设置时间等应有的功能课程设计很有用
lcdfixed
- TEXT LCD lib in C for PIC MCU using PIC CCS for all size
AM2901
- 16为的AM2901的VHDL实现，是一个简单的vhdl实现代码-16-bits AM2901
fir_1
- 这个FIR滤波器是基于ALU框架编写的，仅供参考使用-The FIR filter is based on the framework of the preparation of ALU, the only reference to the use of
cf_interleaver_6_16
- 6*16交织器的实现，非常有用，希望对你有所帮助-6*16interleaver
ps2_uart
- PS2的驱动代码 在串口上有验证 很好的学习资料！-PS2 on the serial port driver code has verified a good learning materials!
three_ADF4350_verilog_code
- 该verilog代码实现对三个ADF4350的控制，并附带一个测试程序。-The Verilog code to achieve control of the three ADF4350, with a test program.