资源列表
alu_32_bit
- verilog 32-bit ALU-verilog 32-bit ALU
traffic
- 交通灯电子钟实现,能应用于实际中...
adder
- 一个verlog hdl 从入门到强化的精通教程-A verlog hdl from entry to the strengthening of the master tutorial
p2s_code
- 并行输入，串行输出模块，输入的位宽在1--16位可变，包括测试平台，自己写的，绝对可用，已经通过modelsim仿真。-Parallel input, serial output module, the input bit-width of 1- 16-bit variable, including the test platform, write your own, absolutely free, Has passed the modelsim simulation.
LCD
- 点亮spartan—3e上的LCD模块 成功显示OK！-Lit spartan-3e success on the LCD module display OK!
booth4
- 4位的booth算法加法器，对计算机组成原理的学习有帮助，verilog语言编写-4-bit adder booth algorithm, the learning of computer organization help, verilog language
alu-10-10
- 16位运算器，包含+、-、与或非、移位等功能，内部指定a、b、cin，输入clk与rst，输出16位y与c\z标志位-16-bit arithmetic unit, including+,-, and or, shift and other functions, within the specified a, b, cin, input clk and rst, 16-bit output y and c \ z flag
UART
- UART (universal asynchronous receiver transmitter protocol) working verilog
uart
- UART模块的verilog代码，经过测试，能够实现正常的接收和发送功能。-Verilog code for UART module has been tested, it is able to achieve normal receive and transmit functions.
sum_of_products
- 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
full_add
- full adder in verilog
FLOAT
- Floating point vhdl coding