资源列表
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- 双四选一数据选择器74LS153,1、写一个程序，用顺序描述语句和并发描述语句（选择信号代入语句或者条件信号代入语句）分别控制74LS153的一个输出端Q。 2、比较一下顺序语句与并行语句各自的优缺点。 输入：逻辑开关。输出：LED灯。 -A double four election data selector 74LS153, 1, write a program, with sequential and concurrent statements describe the sta
ewgweg
- 5959计时器及用数码管显示出来其中包括顶层程序和子程序-5959 timer and digital display including the top-level routines and subroutines
pseudorandom
- 伪随机m序列产生的VHDL语言程序- program in VHDL language for generating pseudo-random m sequence
FIR-VHDL
- 15阶FIR滤波器的设计VHDL代码 ，包括顶层模块及各模块的VHDL设计代码-15 order FIR filter design VHDL code, including the top-level module and each module VHDL design code
Iterative_structure_cordic_verilog
- 迭代结构的cordic算法的硬件代码，基于verilog编写-The structure of cordic iterative algorithm based on verilog writing code, hardware
my_uart_rx
- 该代码实现监测是否有数据接收，若接收到数据，则将数据返回给发送方。-Monitor whether the code data is received, if the received data, the data is returned to the sender.
vhdl_verilog_tutorial
- vhdl 和verilog语言的教学文件，非常简单易懂，适合初学者入门看-vhdl and verilog language teaching documents, very easy to understand, see Introduction for beginners
LcdCtrl
- FPGA控制12864液晶屏，16位总线实现数据及指令发送，配合SPI模块可控制SPI型液晶屏，程序中包含液晶的初始化指令，实际使用过-FPGA control 12864 LCD screen, 16-bit bus for transmitting data and instructions, with the SPI module can control SPI LCD screen, LCD initialization instruction program contains, act
prssdoc
- 代码基于VHDL语言的个文化代码有用的但是可能有错误下在是倾销心-VHDL code based on the cultural code useful but may be under the wrong heart is dumping
jchb
- 递减的三角波 用于输出 是各种信号输出的一种 有较好的精度-di jian san jiao bo yong yu shu chu
DDC_Ver1.0
- 数字下变频（DDC）在如今基于软件无线电的架构中对系统的整体性能决定性的影响，代码为基于Matlab的4通道DDC程序，程序中可以根据需要调节滤波器等参数评估DDC的性能对于使用FPGA实现DDC有较大的参考价值-Digital down conversion (DDC) in today' s architecture based on software radio system a decisive impact on the overall performance of the code
w
- 用VHDL语言设计四位全加器，有低位进位和高位进位。-VHDL language with four full-adder design, there are low and the high binary binary.