资源列表
zhuangtaiji
- 状态机 多种状态的转换 verilog语言编写-Convert verilog language write state machine multiple states
half_adder
- VHDL code for generating half adder
shift_right
- VHDL code for generaring shift register
d_flip_en
- VHDL code for generating D-flip flop
counter
- generating counter using VHDL
quartus9_tst
- 一个比较简单的基于CPLD的数码管显示程序，适合初学者学习，使用Verilog编写-A relatively simple CPLD-based digital tube display program, suitable for beginners to learn to write using Verilog
DS18B20
- 由于18B20时序要求严格，一般不建议采用niosii来实现对他的驱动。本人自己编写的基于NIOSII驱动函数，50MHz主频，保证可用，温度精确到0.0625度。-Due to stringent timing requirements 18B20 generally not recommended niosii to achieve his driver. I have written based on NIOSII driver function, 50MHz frequency, can
ad9516
- 在FPGA上编写的通过SPI总线配置外部PLL芯片AD9516的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 -Configure external PLL chip AD9516 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you w
dac5686
- 在FPGA上编写的通过SPI总线配置外部DAC芯片DAC5686的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 -Configure external DAC chip DAC5686 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you
ltc2183
- 在FPGA上编写的通过SPI总线配置外部ADC芯片LTC2183的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 -Configure external ADC chip LTC2183 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the state machine, you
UART
- 在FPGA上编写的通过UART接口同上位机进行通信的程序，通过板级调试，验证可用。 -Written on the FPGA to communicate via UART interface ditto-bit machine program, through board-level debugging, verification is available.
ADCaPLL
- 在FPGA上编写的通过SPI总线配置外部PLL芯片AD9518和ADC9268的程序，通过板级调试，验证可用。程序通过状态机实现，将需要配置的寄存器值转为SPI总线的数据格式发送出去。 -Configure external PLL chip AD9518 and ADC9268 via SPI bus program on FPGA written by board-level debugging, verification is available. Program through the