资源列表
64QAM_peng
- OFDM的64QAM调制，包含fft 星座映射 还有解调-OFDM-64QAM modulation, demodulation still contain fft constellation mapping
BPSK_peng
- OFDM的BPSK调制与解调,有说明，有需要的朋友可以-OFDM BPSK modulation and demodulation, a note, a friend in need can look
QPSK_peng
- OFDM的QPSK调制与解调,有说明，有需要的朋友可以-OFDM QPSK modulation and demodulation, a note, a friend in need can look
BPSKQPSK16QAM64QAM
- OFDM的调制与解调,有说明，有需要的朋友可以看看，个人著作-OFDM modulation and demodulation, a note, a friend in need can see, personal writings
UART
- Verilog写的串口代码，包括发送和接收，在DE2平台测试通过。-Verilog write a serial port code, including sending and receiving, the DE2 platform test pass.
dianzizhong
- 使用Verilog语言编写的电子钟，课堂小实验，经过测试可用。-Electronic clock, with Verilog language classroom experiments, after testing is available.
EMIF
- EMIF接口调试代码，使用的是Verilog语言，FPGA与DSP通信，测试成功-EMIF interface debugging code that USES the Verilog language, FPGA and DSP communication, testing success
FPAG_REAL_SOURCE
- FPGA实战项目程序，适合进阶和务实的学者。值得拥有！-FPGA for advanced learner
exp5
- 用 VHDL 语言设计一半加器电路，然后用元件例化（COMPONENT）语句调用两个半加器电路，用结构描述实现一个全加器。-Design using VHDL half-adder circuit, and then use component instantiation (COMPONENT) statement invokes two half adder circuit, with the structure described in the realization of a full a
Four-quiz-Responder
- 运用VHDL语言实现四路智力竞赛抢答器。抢答器的主要功能模块是是：1、对第一抢答信号的鉴别和锁存功能；2、计分功能。3、数码显示 ；4、答题限时功能。在本设计主要讲述抢答、计分和警告的功能。-Using VHDL language quiz four Responder.Responder main function modules are: 1, for the first answer to identify and latch signal 2, scoring functio
Four-binary-adder
- 熟悉 VHDL 语言的模块化设计，了解元件例化和打包调用语句。用 VHDL 语言设计一半加器电路，然后用元件例化（COMPONENT）语句调用两个半加器电路，用结构描述实现一个全加器。-The modular design of VHDL language familiar to understand the components and packing cases call statement. Design using VHDL half-adder circuit, and then us
Count-clock-synthesis-experiments
- 练习综合设计能力，设计一个含时/分/秒的时钟，并且可以设置、清除、 12/24 小时工作模式切换。-Exercise comprehensive design capabilities, including the design of a time/minutes/seconds of the clock, and you can set, clear, 12/24 hour work mode.