资源列表
FIFO_altera.v
- FIFO for Altera Cyclone II or Cyclone III on memory blocks. Length of FIFO can be changed.
shifter_8bit
- 利用VHDL语言实现的8bit移位寄存器的设置，可以实现左移或者右移，全部工程都在rar里面，可以直接使用。-Using the VHDL 8bit shift register settings, you can achieve the left or right, all the works are in rar inside, can be used directly.
KEY_down_detect
- 按键检测VHDL程序，主要实现对开发板按键的检测以及一些时间延迟的信息。程序较全，可以按照不同的开发板设置相应的引脚进行操作。-Key detection VHDL program, the main achievement of some time delay detection and information on the development board keys. Than the whole program, you can set the corresponding pin to
spi_dac_ad7394_ad7395.v
- Verilog code of SPI configurator for DAC AD7394 and AD7395
wgy_o1
- 抗干扰接收机程序，包括解调与抗干扰算法-Anti-jamming receiver program
New-Folder-(2)
- UART communication on SPARTAN 6 it contains tx and rx
1
- Verilog语言编写的电话计费器程序-Telephone billing program written in Verilog language!!!!!!!!!!!!!!!!!!! !!!!!!
12
- 用Verilog语言编写的数字时钟程序-Using Verilog language digital clock procedures!!!!!!!!!!!!!!!!!!!!!!!
11
- 用verilog编写的带同步清0、同步置1 的D 触发器；带异步清0、异步 置1 的JK 触发器-Verilog prepared by the synchronous belt, synchronous D flip-flop 0 1 with Asynchronous Clear 0, asynchronous set D trigger 1 with Asynchronous Clear 0, asynchronous set JK trigger 1!!!!!!
test6_timer
- 这是有Quartus II和Nios II共同协作完成的基于FPGA的异步电机矢量控制系统，里面包含定时器，LCD显示，温度检测等内容-This is the Quartus II and Nios II work together to complete induction motor vector control system based on FPGA, contains a timer, LCD display, temperature detection, etc
SDRAM
- verilog编写的SDRAM实验，有串口调试助手和相关资料-Verilog prepared by the SDRAM experiment, a serial debugging assistant and related information!!!!!!!!!!!!!!!!!!!!!
1
- verilog编写的11阶FIR数字滤波器-The 11 order FIR digital filter Verilog prepared!!!!!!!!!!!!!!!!!!!!!