资源列表
DM9000AaPC
- 用verilog语言完成的基于FPGA的DM9000A驱动，完成与PC的10M/100M通信-Using Verilog language to complete the FPGA DM9000A driver based on 10M/100M communication, complete with the PC
Microblaze-bysteps
- this document describes how to create a VHDL project based on Microblaze. ENSIAS Morocco
Actel_DirectCore_CORESPI_4.2.116
- Actel DirectCore CORESPI 4.2.116 Verilog and VHDL RTL source files for SPI controller on APB
00323960
- C to VHDL Converter in a Codesign Environment C2VHDL
816-1681
- SPARC Assembly Language Reference Manual
Pong
- ping pong game fpga DE1
DDS_Core_HSpeed_ADDA_C5H
- 基于FPGA的高速ADDA采集工程源代码，是基于ALTERA公司的CycloneⅡ芯片的工程示例。-FPGA-based high-speed ADDA acquisition project source code is an example of ALTERA engineering based company CycloneⅡ chips.
DM5_VGA_img_C5H
- 基于FPGA的VGA输入采集工程示例，是基于ALTERA公司的CycloneⅡ的EP2C5芯片，具有一定的参考价值。-VGA input sample collection project based FPGA is based on the company s CycloneⅡ of EP2C5 ALTERA chip, has a certain reference value.
DDS_Core_Norml_ADDA_C5H
- 基于FPGA的DDS内核的信号采集和输出，是基于ALTERA公司的CycloneⅡ的EP2C5芯片，是一个很好的参考示例。-DDS core FPGA-based signal acquisition and output is based on the company s CycloneⅡ of EP2C5 ALTERA chip, is a good reference example.
fpga_usb_serial_20131205.tar
- usb serial core is a vhdl synthesizable code, implementing serial data transfer over usb. Combine with a UTMI-compatible transceiver chip, this core acts as a USB device that transfers a byte stream in both directions over the bus
TLC5620_verilog
- LC5620是TI公司的DA转换芯片， 下面的代码实现的简单的DA转换功能。 说明：数码管1显示通道， 数码管2显示RNG值，数码管3和4显示CODE值。按键1切换通道，按键2改变RNG值(0或1)，按键3改变CODE值，按键4未使用。-LC5620 is TI s DA converter chip, simple DA conversion function following code to achieve. Descr iption: a digital display channel,
exercise1
- 使用verilog编写的按键控制数码管的程序，四个拨动开关控制数的进制-Verilog prepared using digital key control procedures, four toggle switch controls the number of decimal