资源列表
kp_lcd
- This is Keypad and LCD interface C code Tested on Sparton 3 xilinx FPGA.
kp_uart
- This UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.-This is UART and LCD interface C code Tested on Sparton 3 xilinx FPGA.
uart_receiver
- This UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.-This is UART Receiver interface C code Tested on Sparton 3 xilinx FPGA.
uart_transmitter
- This UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.-This is UART Transmitter interface C code Tested on Sparton 3 xilinx FPGA.
ideacore1
- This is IDEA encryption Algorithm. Tested on Sparton 3 xilinx FPGA.
iamgod
- this a very nice vhdl program for making shit and stuff... plz write back if any trouble with it-this is a very nice vhdl program for making shit and stuff... plz write back if any trouble with it..
23-10111
- a simple serial to parallel converter using XILLINX and VHDL (the number of the project represents the binary code used by the converter e.g 23- 10111)
PLL
- PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上； 顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is
jpegVerilog
- FPGA实现jpeg Verilog源代码-FPGA realization of jpeg Verilog source code
HDLcodingstyle
- verilog HDL 代码综合风格，非常适合初学者-verilog HDL code integrated style, very suitable for beginners