资源列表
sevensegment
- FPGA-Seven segment and counter
vhdl
- 数码管现实bcd码的解码过程，0000-1001用数码管现实译码结果-Bcd nixie tube reality code
LEDjun
- 此程序能够实现4位二进制乘法，可以放心使用，可能不太全，第一次上传，不大明白-4*4 multiply which can be used that s all.
uart_verilog
- 串口的Verilog源程序，可以用modelsim下进行仿真调试-Serial port of the Verilog source code can be carried out under the modelsim simulation debugging
mc8051_design
- 8051内核的设计，用Verilog硬件描述语言实现，在modelsim环境下进行仿真。-8051-core design, using Verilog hardware descr iption language, in the modelsim simulation environment.
cadence_allegro_teach
- 用CADENCE做VHDL语言实验的教程-CADENCE done using VHDL language course experiment
VHDL
- 数字逻辑基础与Verilog设计,针对verilog语言的特点，讲解了很多例子！-Verilog
UART
- Hardware Design with VHDL Design Example: UART
7-segment
- VHDL Design of BCD to 7-segment decoder using PROM
cymomete
- 采用测频法设计一个8位十进制数字显示的数字频率计。测量范围1-499999hz。-Frequency measurement method used to design an 8-bit decimal figures show that the digital frequency meter. Measuring range 1-499999hz.
shop
- 自动售货机控制系统，具有对货物信息的存储，进程控制，硬币处理，余额计算和显示等功能。-Vending machine control system, with information on goods store, process control, coin processing, the balance of the calculation and display functions.
PSTOLCD
- 此为在xinlix系统上开发的PS通信程序，用VHDL语言开发-This xinlix system in the development of PS communication program, with the development of VHDL language