资源列表
Clk50M_div_1HZ
- 分频实验，将50M时钟分频为1HZ，输出LED1，闪亮-Crossover experiment, 50M clock divider is 1HZ, output LED1, shiny
dled
- 用于动态数码管显示实验，可以看到动态数码管显示 -Dynamic digital display experiment
key_led
- 读取按键信号实验 如果按下的是key1,那么点亮LED1 如果按下的是key2,那么点亮LED1-LED2 以此类推，如果下按key8，那么全部点亮8个led-Read key signal experiment If you press the key1, then lit LED1 If you press the key2, then lit LED1-LED2 So, if the next press key8, then all lights 8 led
Frequency-divider
- 利用Verilog设计的在停车场情况下的模拟的分频器和计数器的代码-The use of Verilog design in the parking lot in case of analog frequency divider and counter code
verilog
- 用verilog设计的寄存器，储存器，锁存器，译码器以及在其中用到的八位串联并联间的相互转换。-Verilog design registers, memory, lock latch decoder and the use of eight series parallel conversion
traffic
- 学习VHDL语言入门程序——交通灯。对理解时序关系和VHDL基本语法很有帮助。-Learning VHDL language entry procedures- traffic lights. Understanding of the relationship between the timing and VHDL basic grammar.
clock
- 利用VHDL语言实现了时、分、秒的计时，并在七段数码管显示出来。-Using VHDL language realize the hours, minutes and seconds of time, and in the seven-segment LED display.
ads822
- 自己用Verilog语言写的ADS822芯片的驱动，亲测可用。其他并行ADC芯片也可以用。-Verilog language used to write their own drivers ADS822 chips, pro-test available. Other parallel ADC chips can also be used.
dual_ram
- 在ISE中测试双端口RAM的源码，结合DDS可以通过Isim仿真直接测试RAM IP核的使用是否正常。-Dual-port RAM test source code in ISE, the binding DDS RAM IP core can be directly tested whether the use of the normal simulation.
camera_bfm
- ov7670摄像头功能总线模型的源代码和源代码仿真-ov7670 camera function bus model source code and source code emulation
crc32
- 该文件主要描述的是crc算法的实现，是8bit输入，输出的是32bit的crc校验码-The document is to achieve crc algorithm described is 8bit input, the output is a 32bit crc checksum
FPGAforlcdDisplay
- FPGA ship FOR LCD display, the LCD is 12864.有兴趣的初学者可以看看，高手绕过。-FPGA ship FOR LCD display, the LCD is 12864 MODEL.