资源列表
FIFO
- FPGA TI DSP的EMIF接口的地址总线问题-FPGA FIFO
sony_ccd
- SONY CCD DIRIVER，VERILOG
qudong
- 实现驱动红外探测器前端图像采集功能，实现红外热成像镜头的前端采集。-Infrared detector drive to achieve front-end image acquisition, to achieve front-end collection of infrared thermal imaging lens.
fifo
- 使用Verilog实现异步fifo的功能-Use Verilog implementation of asynchronous fifo functionality
FIFO
- 同步时钟FIFO已经在FPGA及modelsim中充分验证-Synchronous FIFO has been fully validated
demo8-ps2_1_vhdl
- ep1c3实现ps2 Assembler Status Successful - Fri Aug 27 17:48:36 2010 Revision Name ps2_1 Top-level Entity Name ps2_1 Family Cyclone Device EP1C3T144C8-ep1c3 realize ps2,ep1c3 realize ps2,ep1c3 realize ps2
EP1C3-uart_1_verilog
- EP1C3-uart_1_verilog,程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控制器，10个bit是1位起始位，8个数据位，1个结束位。 串口的波特律由程序中定义的div_par参数决定，更改该参数可以实现相应的波特率。程序当前设定的div_par 的值 是0x145，对应的波特率是9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间划分为8个时隙以使通 信同步.-EP1C3-uart 1 verilog, implements a program
demo3-seg2_vhdl
- ep1c3-seg1_vhdl,７段数码管实验２：递增方式在4位数码管上向上计数显示从0000-0001->0002……..9999….0000….0001…. 设计了一个4位十进制计数器，并用数码管显示当前计数值-ep1c3-seg1 vhdl, 7-segment LED Experiment 2: incrementally on four digital display counts up 0000-0001-> 0002 ...... ..9999 ... ...
VGA_IP
- VGA IP used to connect the FPGA and VGA
AX301
- 黑金FPGA助学版-tcl,包含开发板所有管脚。不需要再对板子管脚定义。AX301-Black Gold FPGA Student Edition-tcl, development board contains all the pins. No need for a board pin definitions. AX301
serial_r
- 串口通信的接收代码，适合工程应用，也适合入门学习，个人调试无问题-Receive Code serial communication, for engineering applications, but also for learning portal, individual debug no problem
Adder_4bit
- Verilog Program for a 4bit Adder