资源列表
Test
- verilog shift register code
SyncFIFO
- dual-port synFIFO with programmable depth and length, course project, do not use for commercial.
MIPS
- 5个stage的pipeline MIPS，支持着JUMP，BRANCH等跳转命令。-simple 5-stages MIPS structure which supports forwarding commands.
spimaster.tar
- SPI Interface Master Control RTL Verilog Code
spi_boot-rel_3_1_rev_C.tar
- SPI Boot Interface Control RTL Verilog Code
Desktop
- code for edge detection
Dijkstra
- 用verilog 实现求最短路的Dijkstra算法，用modelsim仿真通过，数据真确，-Dijkstra implemention with verilog base on FPGA
stopwatch
- A stopwatch circuit that counts minutes and seconds, and has reset, pause functionalities. Designed using Verilog.
FlappyFPGA-master
- Recreation of the game Flappy Bird, with an emphasis on replicating the physics component of the gameplay.
FPGA-Connect4-master
- Source code for an example VGA controller
verilog_projects-master
- Multiple useful Verilog examples including a VGA controller
verilog-tetris-master
- An implementation of the Tetris game using Verilog and a Spartan fgpa board