资源列表
1M_200k_-firstandard
- 1M_200k_低通fir10阶verilog标准代码-1M_200k_ order lowpass fir 10 verilog standard tags
3-ddc-cic_5hb_firmatlab-testbench)
- 三通道上下变频cic_5hb_firmatlab仿真程序-Three-channel down conversion cic hb fir matlab simulation program
fir10order-verilog
- 1M_200k_低通fir10阶verilog标准代码-1M_200k_ order lowpass fir 10 verilog standard tags
2^n-divor
- 2的n次方分频设计，可以实现任意分频。使用verilog编写-n th power of 2 crossover design, you can achieve any frequency. Use verilog to write
OpenMIPS_VHDL_study_v1.0
- 10天实现OPENMIPS处理器-VHDL版[内有详细代码，testbench和设计文档，十天教你学会MIPS架构CPU设计]-10 days to achieve the OPENMIPS processor-VHDL version [within a detailed code, testbench and design documents, ten days to teach you to learn MIPS architecture CPU design]
SIV_ALTMEMPHY_DDR3
- ddr3 interface demo,
OOO
- AES 低资源利用率的加密解密，状态机的使用，128位的-Encryption and decryption, the state machine of low resource utilization using AES 128-bit
uart_fifo_transceiver_verilog
- verilog UART FIFO 自发自收 自己验证过 基于EP1C3T开发板的-Verilog UART FIFO internal loopback； tested； based on EP1C3T
cp_model
- 原创协处理模型，异步并行接口，verilog实现，可作为仿真testbench用 -Co-processing model, asynchronous parallel interface, verilog achieve, can be used as a simulation testbench
New-WinRAR-archive.RAR
- 250NM CMOS TSMC MOSIS PARAMETERS
count_5
- 5路光栅信号的数字滤波、四倍频、同步锁存、计数-5-way digital filtering raster signal, quadrupled synchronous latch count
fangbo
- 将运动控制卡的方向信号与脉冲信号转换为两路正交方波信号信号（模拟光栅信号）-The direction of the signal and the pulse signal is converted motion control card for two orthogonal square wave signal signal (analog signal raster)