资源列表
ethernet_test
- 以太网FPGA通信,verilog代码，实现双向通信-Ethernet FPGA communication
QD
- 四路抢答器，主持人复位之前抢答算做犯规，复位之后抢答第一个人有效，其余无效。并且均有组别显示与声音示警。-Four Responder, Responder counted reset before the host foul, the first person to answer in an effective after a reset, the rest is invalid. And have a group show with the sound warning.
qdjs
- 10s倒计时，在复位高电平期间，开始倒计时，有某信号(抢答信号)输入，则恢复到10s并保持，准备下次计时。-10s countdown, at a high level during reset and start the countdown, there is a signal (answer signal) input, then back to the 10s and remains ready for the next timing.
ug612
- xilinx的时钟约束指导，适合新手学习-xilinx clock constraint guidance documents for novices to learn
FULL_ADD
- 编写一位全加器的程序，生成器件后用BLOCK画出bdf图，最终成为四位全加器。此为实验报告，里面包括原理及框图及源程序。-Preparation of a full adder program, after generating device using BLOCK draw bdf map, eventually become four full adders. This is a test report, which includes the principle and block diag
xilinx_license_2015
- Vivado Design Suite v2015.4版本license-the license of Vivado Design Suite v2015.4
uartlvds
- UART VHDL sources with FIFO-UART VHDL sources with FIFO,baudrate,receiver,transmitter,register,testbench
conv_encoder(rate=1_2)
- 这是用ISE编写的verilog语言1/2码率的卷积编码的代码-It is written in verilog language ISE convolution coding rate 1/2 code
anish-bit-masking
- vhdl code for bit masking algorithm
05413cordic
- VHDL CODE FOR CORDIC ALGORITHM
pll_prj
- PLL配置仿真实验 PLL，即锁相环。简单的理解，给PLL 一个时钟输入（一般是外部晶振时钟）， 然后经过PLL 内部的处理以后，在PLL 的输出端口就可以得到一定范围的时钟频 率。其之所以应用广泛，因为从PLL 输出得到的时钟不仅仅从频率和相位上比较 稳定，而且其时钟网络延时也相比内部逻辑产生的分频时钟要小得多。-Altera FPGA Cyclone
AX301_led_test_code
- 黑金AX301开发板led相关实验程序代码-AX301 development board LED test code