资源列表
timer
- 淺顯易懂的學習verilog程式基礎範例以時鐘為示範-Learn easy to understand the basic Verilog code for an example of a clock model
top
- RS232串行通信，采用VHDL编程，由波特率发生器，接收器和发送器构成-RS232 serial communication using VHDL programming, by the baud rate generator, receiver and transmitter constitute
digital_clock
- 实现嵌入式系统的秒表计时，时间显示和闹钟功能-Implementation of embedded systems stopwatch timer, time display and alarm clock function
vhdl
- vhdl codes for combinational and sequential circuit
EDAstar
- 对微电子的学习和FPGA的开发设计很有帮助-learn and use VHDL
VerilogHDL
- Verilog HDL的开发学习教程。值得一看，学FPGA的朋友。-Verilog HDL Development Study Guide. Worth a visit, learn FPGA friends.
DesignReuseMethodology
- 本文介绍了在进行FPGA设计，特别是SOC设计时，为了保证顺利移植，重新利用原有程序，而应该注意的一些基本问题和方法，本文由xilinx提供，但对所有的FPGA的使用者都有非常好的借鉴意义。-In this paper, during the FPGA design, especially in SOC design, in order to ensure a smooth transfer, re-use of existing procedures, but should pay atten
USNavyVHDLModellingGuide
- 美国海军原版VHDL编程指南，其严谨的代码风格和编程规范值得大家认真学习-U.S. Navy original VHDL Programming Guide, and its strict code and programming style norms everyone deserves serious study
DDR
- leon ep2s60 ddr use altera statix2 and add ddr sdram-leon ep2s60 ddr
20090224fpga
- 《数字信号处理的FPGA实现》代码，数字信号处理一些算法的FPGA代码，比较全-" Digital signal processing FPGA implementation" code, digital signal processing FPGA code some algorithms to compare the whole
rs-codec-8-16
- RS[255,223]纠错码verilog源码，包含编码和解码模块，以及testbench等。-Verilog source code for RS[255,223] encoder and decoder, with testbench included.
stereo_vision
- Stereo-Vision circuit descr iption, Aug 2002, Ahmad Darabiha This design contains four top level circuits: sv_chip0.vhd, sv_chip1.vhd, sv_chip2.vhd and sv_chip3.vhd each of them built by one Virtex2000E fpga chip. This design is hierarchical an