资源列表
VHDL-8031-IPCore
- this a ipcode of 51 mcu!-this is a ipcode of 51 mcu!
afg
- this is a docoument of education!
boothmultiplier
- verilog code for 8-bit signed integers....its working
key
- 键扫描 处理程序 verilog 使用时钟为50Hz // 低电平为按下,高电平为断开 // 输出状态,1为键入,0为无键-Key scanning process using the clock for Verilog 50Hz// low level for the press, high for the disconnect// output state, one for the type, 0 for no key
divisor_ITA_VHDL.tar
- Divisor do Tipo com restaura莽茫o sequencial
modelsim_ddr2sdram_spartan3s700an.tar
- Modelsim DDR2 SDRAM files
ddr2sdram_spartan3s700an.tar
- It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Spartan 3AN Starter Kit - Diligent fully working.-It is a first time code being developed to designers who want to get your DDR2 SDRAM on-board in Sparta
32-bit_multiplier_model
- 32-bit_multiplier_model程序，可以直接拿来使用-32-bit_multiplier_model procedures, can be directly used to use
ARM7_core
- ARM7内核,vhdl源码形式，不可多的的好东西。-ARM7 core, vhdl source code form, not the many good things.
daout-Sine-wave
- 正弦波的vhdl输出，使用VHDL编写的，已经通过调试-Sine wave output of the VHDL, the use of VHDL prepared already through debugging
AlteraSDR-SDRAM
- Altera 官方提供的SDRAM控制器,verilog的-SDRAM controller provided by Altera in Verilog HDL
master_verilogHDL
- < 精通VerilogHDL IC设计核心技术实例详解>>一书的附录源代码。-< < Proficient in core technology VerilogHDL IC design examples explain> > Appendix 1 of the book source code.