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  1. FPGA4U

    0下载:
  2. 采用Altera公司的CycloneII芯片EP2C8的一些程序代码。-The use of Altera Corporation CycloneII chip EP2C8 some program code.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-14
    • 文件大小:3.39mb
    • 提供者:熊小姐
  1. sd_card

    0下载:
  2. 在开发FPGA上比较有用,主要关于SD CARD的源码-FPGA in the development of more useful, the main source of about SD CARD
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-06-19
    • 文件大小:25.21mb
    • 提供者:田景
  1. statment

    0下载:
  2. 在VHDL的设计中用for 语句来实现2 个8 位数的相乘计算。-In the VHDL design using for statement to achieve two-digit multiplication calculation 8.
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:2.28kb
    • 提供者:
  1. UART_for_FPGArar

    0下载:
  2. it is a verilog code written for MELAY state machine based UART and it wll synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device]-it is a verilog code written for MELAY state machine based UART and it wll
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-29
    • 文件大小:5.45kb
    • 提供者:yasir ateeq
  1. traffic_controller

    0下载:
  2. it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].it is a state machine based code.-it is a verilog code written for traffic light controlle
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-28
    • 文件大小:34.65kb
    • 提供者:yasir ateeq
  1. FIFO

    0下载:
  2. it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-03-30
    • 文件大小:30.81kb
    • 提供者:yasir ateeq
  1. digital_watch_FPGA

    0下载:
  2. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-13
    • 文件大小:1.96kb
    • 提供者:yasir ateeq
  1. ADC_INTERFACE

    0下载:
  2. it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit. -it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in xinlix i
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-15
    • 文件大小:6.7kb
    • 提供者:yasir ateeq
  1. ff_mul

    0下载:
  2. 伽勒华域乘法器用于RS编码中,用verilogHDL语言实现-Galle Hua domain multiplier for RS encoding, the implementation language used verilogHDL
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-11
    • 文件大小:1014byte
    • 提供者:dahai
  1. Disturb

    0下载:
  2. 适用于初学者的一个m序列扰、解码器-Apply to beginners as a sequence of interference m, the decoder
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-24
    • 文件大小:185.16kb
    • 提供者:张晓勃
  1. UART_SUCCESS

    0下载:
  2. 实现FPGA和上位机的串口通信,里面由波特率发生器,移位寄存器,计数器,detecter,switch,switch_bus等功能块综合而成。-FPGA implementation and the host computer' s serial communication, which by the baud rate generator, shift register, counters, detecter, switch, switch_bus such as function bl
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-05-08
    • 文件大小:1.77mb
    • 提供者:zhn
  1. io_lvds

    0下载:
  2. xilinx LVDS接口程序,xilinx LVDS接口程序-xilinx LVDS interface program,xilinx LVDS interface program
  3. 所属分类:VHDL-FPGA-Verilog

    • 发布日期:2017-04-17
    • 文件大小:122.08kb
    • 提供者:s
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