- ConvertEMFToBMP_demo 将图形文件的格式从EMF转换为BMF的工具
- Classic_php_code_management_system_development_and php开发设计管理系统经典代码Classic php code management system development and design
- iso-SE-Template 详细的软件工程开发过程指导规范
- CSharpIE 基于C#编程的模拟IE浏览器程序
- The-three-layer-architecture 把ADO.NET用三层架构来显示
- piusen_v35 最大似然（ML）准则和最大后验概率（MAP）准则
资源列表
FPGADFPlabfiles
- 如何使用ISE和FPGA使用指南里面附带许多实验-How to use the ISE and FPGA UserGuide, which fringe much experimental
lift
- VHDL driver of lift in building. Result is presents on LED segments[decimal value].
counter
- Decimal counter which is counting from 256 to 0. After that there will appear logic "1" in out. You can stop counting by pressing sequence. I called it detonation clock :]
ring
- Ring register[1 from 8] which seven speeds. The result is presented on 8 LEDs. After every cycle, speed grows. The process starts again after last 8 cycle.
word
- Code was successfully implemented within ALtera FPGA with Quartus 6.0. It presents two polish own female names: ULA and ALA whose are scrolling on the 4-columns crystal LED. When you press the switch it will turn from ULA into ALA and continue scroll
cross_street_lights
- Cross street lights driver in VHDL. It have been tested on XILINX 9500.
halfband
- verilog写的39阶通带为20KHz的半带fir滤波器，经测试正确。-verilog halfband FIR
jc2_vhd
- JC2_VHD is a bi-directional 4-bit Johnson counter with stop control
freqm
- a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display
gold_code_vhd_217
- Gold Code Generators in Virtex Devices
pong
- Pong is a mixed schematic, VHDL, Verilog project featuring the PS2 and VGA monitor connections of the Xilinx\Digilent Spartan-3 demo board.
DW_8b10b_enc.v.tar
- amba ahb protocol with test benches