资源列表
rd_wr_control
- USART coded in VHDL. It is writted in 5 files. I am uploading the files in order.
stopwatch
- 基于fpga的停表设计vudl编写，使用vhdl编写的.v文件。-the stopwatch based on fpga written with vhdl
usart_verilog
- Uart verilog 代码 可综合 很好的代码-Uart verilog code
simple_spi.tar
- Enhanced version of the Serial Peripheral Interface available on Motorola s MC68HC11 family of CPUs.Enhancements include a wider supported operating frequency range, 4deep read and write fifos, and programmable transfer count dependent interrupt gene
miniuart.tar
- Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost eve
oc8051.tar
- 8051 core writen in VHDL, fully functional and tested
Avalon_VGA_Controller
- Vga Controller source code for Altera FPGA
19854799dul_ram(yk)
- 双口RAM的FPGA源码Altera 活XIinx或ATmel公司都可以-Dual-port RAM of the FPGA source
VHDL_FPGA_design
- VHDL FPGA 设计流程，基本原理和方法，比较全面。-FPGA VHDL DESIGN
VHDLlanguage
- VHDL语言详解，详细描述了VHDL语言设计规范，有帮助哦-VHDL LANGUAGE DESIGN
VHDL_GOLD_BOOK
- VHDL黄金宝典，VHDL设计的好助手，看看吧-VHDL GOLD BOOK,CLASSICAL RULL ABOUT THE VHDL DESIGN
VHDL_BASIC_CONCEPT
- VHDL 基本概念，有助于帮助初学者快速理解VHDL基本概念和内容，快速掌握。-VHDL BASIC CONCEPT,which discribes the basic concept of the vhdl design.