资源列表
bingchuan2
- verilogHDL编写的并串转换模块，在ISE软件中仿真过，可综合，绝对是正确的-prepared and verilogHDL string conversion module, the ISE simulation software that can be integrated, is absolutely correct
bingchuan
- verilogHDL编写的并串转换模块，在ISE软件中仿真过，可综合，绝对是正确的-prepared and verilogHDL string conversion module, the ISE simulation software that can be integrated, is absolutely correct
uart
- 基于FPGA的uart源代码，异步串行通信，vhdl书写的。-uart codes。write with vhdl.
Codingexperimentcrcdcord
- 编码实验Your use of Altera Corporation s design tools, logic functions and other software and tools, and its AMPP partner logic -Coding experiment
stamp_seller
- 一个自动售邮票的控制电路。 用两个发光二极管分别模拟售出面值为六角和八角的邮票，购买者可以通过开关选择一种面值的邮票，灯亮时表示邮票售出。用开关分别模拟一角、五角和一元硬币投入。用发光二极管分别代表找回剩余的硬币。 要求：每次只能售出一枚邮票；当所投硬币达到或超过购买者所选面值时，售出一枚邮票，并找回剩余的硬币回到初始状态；当所投硬币值不足面值时，可以通过一个复位键退回所投硬币，回到初始状态。-An automatic control circuit sell stamps. With
subadd
- 一个四位二进制加/减运算器。 要求：当控制端G＝0时做加运算，G＝1时做减运算。用发光二极管表示运算结果的正、负。用数码管显示运算结果：加运算时，相加之和不超过15，减运算时，结果可正可负，但都用原码表示。-Plus a four binary/by calculator. Requirements: When the control terminal G = 0 when computing increases, G = 1 when computing reduced. Computin
clk_div
- Clock division document
I2C_Master
- I2C program (Inter IC bus)
pwm
- Pulse width modulation
UART
- Universal async Transmitter Receiver
VHDL_Hardware_Language
- vhdl硬件描述语言，对于进行FPGA、CPLD开发的人来说比较有用。-vhdl hardware descr iption language is fundamental to the FPGA, CPLD development of more useful people.