资源列表
multier
- 利用图元实现层次化设计,编程完成数字序列的乘积求和-The realization of the use of pixel-level design, programming to complete the product sum of the number of sequences
brentkung_32
- 32 bit brentkung adder tr-32 bit brentkung adder tree
koggestone_32
- koggee stone 32 bit adder
CSLA_32
- 32bit carry select adder
mp
- this the vhdl code of arithmetic and logic unit of 16 bit microprocessor.-this is the vhdl code of arithmetic and logic unit of 16 bit microprocessor.
hadder
- 这是一个8位全加器，利用vhdl完成了电路的构成，-this is a 8 bit adder,
A01
- 利用XC9572-TQFP100(Xilinx CPLD)制作的多功能CPLD/FPGA的ISP下载线源代码及线路图。可用来烧录Xilinx,Lattice,Altera等厂家的CPLD/FPGA.-Using XC9572-TQFP100 (Xilinx CPLD) produced by multi-CPLD/FPGA download cable ISP in the source code and circuit diagram. Burning can be used to Xilin
Multi_Debug_Card
- 利用Xilinx XC2C128（Xilinx CPLD）制做的台式电脑的Debug卡及原理图，对于不开机的主板，能侦测出CPU到北桥之间具体那根信号线空焊，用于快速维修不开机之主板。-The use of Xilinx XC2C128 (Xilinx CPLD) desktop computer system to do the Debug Card and schematic diagram for the motherboard does not boot, can detect the
guard_against_theft
- 利用XC9572－PQ44（Xilinx CPLD）制作的一款家用防盗报警器的Verilog源代码及原理图，当房门打开后，15秒内若没有按下Key1,则会自动拨打设定手机号（当然，要另连接一台手机）-Using XC9572-PQ44 (Xilinx CPLD) produced by a home burglar alarm of the Verilog source code and the schematic diagram, when the door opened, within 15
bin2bcd
- Binary to BCD converter
testMem
- Example of a FPGA memory controler
EDA
- 用VHDL语言编写的时钟显示的源程序代码-VHDL language used to display the clock source code