资源列表
second
- 关于VHDL写的秒表程序，有模块，顶层文件，仅供参考-On the stopwatch to write VHDL procedures modules, top-level documents, for reference only
ncr
- module to wait 2 clocks for SD card
wait_data
- module to wait data on DAT line SDIO mode
FiltroDSP
- This sources implement a 8-bit FIR Filter with selectable coefficent rom.
MultiplicadorSHIF
- This code creates a 8 bit full multiplier.
dds
- 利用EDA硬件描述语言来实现DDS功能，利用VC++6.0实现sinx,cosx数据的采集，用quart2软件为载体实现-The use of EDA hardware descr iption language to achieve the DDS functions, using VC++6.0 to achieve sinx, cosx data collection, software used as the carrier to achieve quart2
uart_regs
- uart_regs core目录下为Altera的IP宏功能模块-Altera IP uart_regs core
Project
- 定制一个双端口RAM，DualPortRAM-RAM，DualPortRAM
Project
- 熟悉Altera IP的产生和实现方法定制一个8B10B编码器- 8B10B codeer
source
- ModelSim对Altera设计进行功能仿真的简单操作步骤-modelsim simulation
FHT_example
- Altera FPGACPLD FHT_example design
Example-s2-1
- 其中的EPLL、MY_DQ和MY_DQS模块是用Altera的IP产生器MegaWizard产生的-EPLL MY_DQ MY_DQS