资源列表
touch_screen_verilog
- 一段用于在触摸屏上显示内容的显示代码，可帮助朋友解决一些需要在触摸屏上进行显示的问题-Touch screen display code
switch
- It is switch design (RTL) implemented in verilog and have a verification environment in verilog
counter
- 利用fpga实现秒表。秒表有开始停止，清零的功能-FPGA implementation using a stopwatch. Have begun to stop the stopwatch, Clear function
da_filter
- DA，分布式算法的FILTER滤波器的设计，verilog设计与实现-DA, distributed algorithm of FILTER FILTER design, verilog design and implementation
DF_counter
- 计数式数字频率计，10Hz-10MHz以KHz为单位显示，六位数码管显示，有小数点及溢出标识，1s、0.1s、0.01s闸门时间可选-Count type digital frequency plan, 10 Hz-10 MHz to KHz for unit shows, six digital tube, showed a decimal point and overflow logo, 1 s, 0.1 s, 0.01 s gate time can be chosen
UP3_CLOCK
- 用vhdl编写的时钟 主要实现了时钟功能时间调教功能有待实现 -prepared using VHDL clock main function of clock time tuning function to be achieved
fifoi
- 基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控-Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable
FPGA_Interview_Book_Title
- 在信威dsp软件面试、汉王笔试、扬智电子笔试、新太硬件面题时的题目-Xinwei dsp software in the interviews, written Hanwang, ALi electronic written, the new hardware side too, when the topic title
r429
- 另一个读429码操作IP,对军工时很有用,希望有人喜欢!
verilog_testbench_genetator
- 这是一个perl程序 只需要在cmd中运行，参数为你的Verilog名字 功能是:半自动生成Verilog的testbench，提高编码效率-#-----READ ME of verilog_tb_generate.pl----------------------| # | #-----copyright(C) Xzmeng 2010---------------
VGA_640480VGA
- 640480VGA 控制器 （使用VHDL硬件描述语言，通过Altera QuartusII 开发）-640480VGA controller (using VHDL hardware descr iption language, through the development of Altera QuartusII)
PS2
- 原创！FPGA通过PS2键盘输入，在数码管显示输入。-Original! FPGA via PS2 keyboard input, the digital display inputs.