资源列表
spigpio
- or1200 spigpio core code
adder
- 设计一个16×16位的流水线乘法器。 乘法器部分采用16×16进位保留（Carry-save）阵列构成。 最后一行部分积产生单元要求采用超前进位构成。 -Design of a 16 x 16 pipelined multiplier. Multiplier by 16 x 16 carry save array ( Carry-save ). The last line of the partial product generation unit requires u
led
- 控制8个发光二极管中的一个发光二极管发光，其它7个发光二极管都出于截止状态，发光二极管的导通顺序按照向左或向右两个方向移动，并且通过按键控制发光二极管循环发光移动的方向。-Control of a light-emitting diode light-emitting eight light-emitting diodes, the other seven light-emitting diodes for the cut-off state, light-emitting diode cond
ledseg
- 这是一个数码管的ip核，只需将想要显示的值写进对应的apb寄存器就可在对应的数码管上显示-This is a digital tube of IP core, you only need to want to show the value of the written into the corresponding apb register can be displayed on the corresponding digital tube
halfadder
- 实现全加器的不可或缺的东西，半加器，功能就是为了全加器做好准备-halfadder
jcb
- 递加的三角波 用以输出是各种信号的一种 精度比较好-di jia san jiao bo yong yi xian shi shu chu shi ge zhong xin hao de yi zhong
FFT-transform
- 64位FFT变换源代码，仅供参考。此为单一模块文件，自行建立工程编译-64 FFT transform source code, for reference only. This is a single module file, create your own works compiled
cordic
- CIC滤波器源码，有VERILOG写的，非常有用哦
spi_master
- SPI master code: generates CS and tx/rx data
pll_clock
- 自己写的时钟提取逻辑。用于时钟恢复电路。-Write your own clock extraction logic. For the clock recovery circuit.
CLOCK
- 电子钟的VHDL源码，希望对大家有所作用，是自己编写的。-The VHDL source clock, we hope to effect that I have written.
ldpc-decoder-code
- Specify the decision method used for decoding as one of Hard decision | Soft decision . The default is Hard decision . When you set this property to Hard decision , the output is decoded bits of double or logical data type. When you set this property