资源列表
mini_fifo
- 另外一个用VHDL源码编写的FIFO模块程序,可以比较一下和FIFO有什么区别.-Another, prepared by using VHDL source FIFO module procedures, you can compare and What is the difference between FIFO.
traffic-lights
- 使用Xilinx公司的XC95288XL芯片实现交通信号灯的控制-XC95288XL using Xilinx s chip control traffic lights
pmd
- freeDev Nios 2.1的跑马灯程序，是用verilog HDL 写的，希望对初学者有用-freeDev Nios 2.1 The Marquee program is written in verilog HDL, in the hope be useful for beginners
CRC-32
- 一个关于32位循环冗余校验的verilog代码-A 32-bit cyclic redundancy check on the verilog code
Programmable-source
- 可编程源代码，基于Verilog的程序，西电2013秋学期最新版上课要求自编的程序，txt文件-Programmable source code, Verilog-based program, Western Electric 2013 autumn semester class requires the latest version of the program self
RS232_project
- 串口通讯 rs232 verilog程序，一次接受传送8bits-rs232 verilog project，reciver or trancimiter 8 bits onece
e1framer_latest.tar
- it is very useful and open source but it is not complete
verilog18b20
- DS18B20操作，verilog HDL-DS18B20control，verilog HDL
CRC-CCITT_3c120
- EP3C120硬件下的NIOSii运行，经过测试ok，CRC校验源码。-A table-driven implementation of CRC-CCITT checksums.
top
- 脉冲多普勒雷达回波信号相干积累的VHDL源程序-pulse Doppler radar echo signal coherent accumulation of VHDL source
clock-a-stopwatch
- 基于DE2-70平台，可实现功能： 1、在LCD上显示时间 2、在数码管上显示跑表-DE2-70-based platform, enabling functions: 1、display time on the LCD 2、display stopwatch the digital tube
BramComCtrl
- xilinx FPGA BramComCtrl source.