资源列表
ad cvtor
- 开发环境：maxplus2 a/d convortor-development environment : maxplus2 a / d convortor
encode RS（255，239）编码
- Verilog HDL代码，RS（255，239）编码，未采用弱对偶基-Verilog HDL code, RS(255,239)encoder, without weak-dual base
top_pnadd32
- 32位元浮点数加法器,用于以VHDL编写的32位元CPU-32 bits floating-point Add
cpu
- 32位元浮点CPU,用VHDL语言以类似组合语言的方式写成-32 floating-point CPU(VHDL)
fft
- 用FPGA编程实现fft算法，在maxplus2环境下实现，好用-Fft algorithm with FPGA programming, in maxplus2 environment to achieve, easy to use! !
ideacore1
- This is IDEA encryption Algorithm. Tested on Sparton 3 xilinx FPGA.
Dchufa
- 使用硬件描述语言设计的D触发器，现代逻辑器件-Using hardware descr iption language design of the D flip-flop, the modern logic
alarm-clock
- 基于vhdl的数字闹钟的设计。可实现计时、闹钟、调节时间功能。可以在FPGA上实现。-VHDL-based digital alarm clock design. Can achieve a time, alarm clock, adjust time function. FPGA implementation can be on.
32-bit_multiplier_model
- 32-bit_multiplier_model程序，可以直接拿来使用-32-bit_multiplier_model procedures, can be directly used to use
IIC
- 基于VERILOG HDL的IIC设计，比较基础，设计适合初学者-IIC INTERFCAE DESIGN
flash
- FLASH 读写模块，用于一般通信当中。包括各个状态模块的转化，以及初始化。-Flash reader module to be used for general communications. Including the transformation of the status module and initialize.
SBcalculator
- fpga简易二进制输入十进制输出计算器，八位拨码开关输入，四位数码管输出。开发板：Spartan 3E XC3S100E CP132 -5-A simple binary-decimal calculator. Spartan 3E XC3S100E CP132 -5