资源列表
divider
- verilog HDL编写的浮点除法器，编译通过，可综合。压缩包包含三个文件。-verilog HDL write floating-point divider, compile, can be integrated. Archive contains three files.
freq_high2low
- 输入一个高频时钟，输出一个频率可设置的周期信号的verlog模块，在系统设计时很方便-Enter a high-frequency clock, the output frequency can be set up a periodic signal verlog modules, system design at a very convenient
la_usb-SPISRAM
- 有关到SRAM的VHDL程序,也涉及到USB接口，希望对大家有所帮助
mul8x8
- 8位无符号数与8位无符号数的乘法的VHDL源代码
Printer
- The internal circuit of the simulated printer module, in a students course design - A parallel output controller (POC) .-The internal circuit of the simulated printer module, in a students course design - A parallel output controller (POC) .
adder
- adder subtractor porgramme
URAT
- URAT的VHDL设计及时序仿真、调试、测试。含有波形图
32-bit_multiplier_model
- 此程序为32-bit乘法器，另附有VHDL测试程序-This procedure for 32-bit multiplier, followed VHDL test procedures
DMA
- VHDL code of DMA controller
motor
- this file is vhdl code of motor
EMP1270
- vhdl spi通讯十分好用，可以对AD7634进行spi通讯！-vhdl spi comment
iic_func
- 驱动EEPROM （24LC32）。单字读写代码-Drive EEPROM (24LC32). Single word read and write code