资源列表
s_fifo
- 一个verilog语言描写的同步fifo,包括:Fifo using declared registers for storage和Fifo using (model of) standard memory chip for storage.两种方式,包含testbench
Kbtestbench
- VHDL编写的Keyboard control使用ps2 keboard来使fgpa的led上显示键盘的二进制代码，用4个7seg来显示0-9的数字，该程序包含testbench.-ps2 keyboard controller which could enable led on fgpa to show the binary code of each key on ps2 keyboard and another four 7segment will display the number fr
I2C
- I2C控制，整理优化后的代码（C语言）。-I2C control, finishing optimized code (C language).
Function_clock_generate
- 基于FPGA实现的实时闹钟，在DE2—115开发板上通过验证，实现报时，定时，时间调整等功能-Based on verified DE2-115 development board FPGA to achieve real-time alarm, timekeeping, timing, time adjustment
ourdev_536707
- AVR硬件TWI（I2C）读写PCF8563和AT24C64的源程序-AVR hardware TWI (I2C) and the AT24C64 the source code to read and write PCF8563
I2CLOADER
- I2C Loader VHDL for using a wolfson wm8742 audiochip. as clock you have to use a 50-mhz-clock and devide it by 128
I2C_receiver
- 自己写的一个i2c slave的模块，verilog，已经通过验证，可以写可以读，希望对大家有用-To write a i2c slave module, verilog, has been validated, you can write can be read, in the hope that useful
plc
- plc bus 64 bit tx with rs232(8bit at a time)
rs232
- verily 串口rs232代码，可参数化波特率-uart code in verilog
unsigned_4_adder
- 通过vhdl语言实现四位无符号数的加法，四位拨位置数，用数码管输出结果
dctidct
- dct and idct code for verilog