资源列表
DctInH264
- 这个是华清远见 高级班 培训的 实验 代码(vhdl)
HG_chufaqi_clajiafaqi
- VHDL基-16位的无符号除法器，超前进位加法器可改位数。-VHDL-based-16 bit unsigned divider, CLA can be the median.
bus_multiplex_6to1_upld
- 利用vertex5 FPGA内部DSP48E做高速六通道数据总线切换Verilog-bus switching using DSP48E in Vertex-5
freq_m
- 基于FPGA的verilog语言编写的频率计-Meter based on the frequency of the FPGA verilog language
statment
- 在VHDL的设计中用for 语句来实现2 个8 位数的相乘计算。-In the VHDL design using for statement to achieve two-digit multiplication calculation 8.
cpu
- 16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL
mach_test_ok
- verilog曼切斯特编码解码的FPGA实现-verilog Manchester encoding and decoding on FPGA
apb
- These are the files of apb verification environment. Some of them are useful as a reference for creating the other verification environment.
cfft
- vhdl code for cyclic cfft
DS18B20
- verilog 写的ds18b20控制器-verilog write ds18b20 controller! !
signalgen
- 可调信号发生器，用于产生正弦波，方波，三角波和锯齿波-Adjustable signal generator used to generate sine wave, square wave, triangle wave and sawtooth
codes
- 5 simple verilog codes: Arithmetic.v - arithmetic operations on verilog Accumulator.v - 8 bit adder accumulator counterfpga.v - 4 bit up counter w/ fpga code UpDown3.v - 4 bit Up-down counter w/fpga code pattefier.v - pattern/sequence ident