资源列表
code
- spi接口 实现spi的传送 包括主从模式，时钟的建立。和数据的传送三部分-spi code very good for spi
KEY_IP
- 4X4 矩阵按键的ip核 fpga 测试通过-4 x4 matrix key IP core nuclear test by fpga
nfc
- 近场通信的verilog描述，包含向量名定义，顶层设计等等的精确描述-Verilog descr iption of near field communication, including the vector name is defined, an accurate descr iption of the top-level design, etc.
SF_table_interface
- switch fabric部分代码: fabric和table management 的数据交换. Mac address 从afifo输入, 查询的结果:output port number 存于pfifo中-switch fabric part of the code: fabric and table management data exchange. Mac address from afifo input, the results of inquiries: output port n
shift8
- 一个简单的移位寄存器。VHDL语言的，或许会对你有所帮助！-A simple shift register. VHDL language, and perhaps will help you!
I2cSlave
- I2C slave, I2C slave,-I2C slaveI2C slave,I2C slave,
FPGA_UART
- 在Verilog环境下，实现多个串口的功能，支持波特率，数据位，停止位可设。-In Verilog environment, to achieve multiple serial ports, support for baud rate, data bits, stop bits can be set.
blk_write
- verilog 块ram写入操作 fpga xilinx ip core-Verilog block_ram module fpga xilinx ip core
source
- 4个功能模块是独立操作的。由于输出在时间上不同，在肉眼中才会看到流水灯的效果。用现实的角度去思考的话，宛如有四个局内人，无不关系，各自只是按照自己的节奏完成自己的工作。在局外人的眼中，他们如同有默契般，不需要“指挥者”也能完成任务。-led parallel countrol
VHDL-radar
- 脉冲多普勒雷达回波信号相干积累的VHDL源程序-Coherent pulse Doppler radar echo signal accumulation VHDL source code ，it is easy to use
MIPS-Parts
- // * Data Memory and IO: This is the data memory, and some IO hardware // * 8x16 register file: eight 16-bit registers // * 16-bit ALU // * 2:1 16-bit Multiplexer // * Sign extender from 7 to 16 bits // * 4:1 16-bit Multiplexer-// * Data Me
baugh-Wooley
- baugh Wooley 阵列乘法器 待测试代码 -baugh Wooley multiplier