资源列表
Median-implemnt-baseline-drift
- 工程文件中代码是通过中值滤波算法实现基线漂移-Project file code median filtering algorithm by baseline drift
project_E05_124
- 8 bit computer. Here fore instruction can load to the program counter.Code is written using Xlinx ISE and tested using test bench. Four instructions are load, move, add and sub.
SDH1
- SHD 详细设计,包含各种文档，以及VERILOG 源代码-SHD detailed design, including all documents
AD0804LC
- 使用VHDL语言完成了ADC0804程序,设定阈值，过阈值报警。附带了整个工程文件-with VHDL language,it can work with ADC0804
qiangdaqi
- 电子抢答器 可以容纳四组参赛队进行比赛具有强大信号和锁存能力 自动计分 犯规减分- answerphone
all_use.rar
- all_use.rar
VGA_PS2
- 使用键盘控制显示器上矩形框的移动。使用verilog HDL编写。已经在spartan3-E开发板上实现。保证好用。-Use the keyboard to control the movement of the display rectangle. Prepared using verilog HDL. Has been achieved spartan3-E on the development board. To ensure ease of use.
FPGA VGA
- 游戏代码
vga_game_demo
- 基于FPGA的乒乓球游戏参考设计-FPGA-based reference design table tennis game
ddr2_sdram_latest[1].tar
- ddr2 sdram 控制器的vhdl源码,并包括了ddr2 sdram芯片的仿真模型-DDR2 sdram controller VHDL source code and ddr2 sdram simulation module
ddc_virtex5
- 数字光纤直放站上使用的V5一级变频系统，是其基带板的核心-V5-level inverter system used on the digital fiber optic repeater
zyled
- 采用EDA技术，在quartus2上实现了交通信号灯自动控制器，性能良好-EDA technology used in quartus2 to achieve a traffic signal controller, good performance