资源列表
Altera
- Altera公司内部培训资料，含有多分权威PDF资料，入门提高一步到位。-Altera internal training materials, the authority of PDF data with multisection, started to improve in one step.
Ethernet
- 简易以太网测试仪，连接CPU和传输物理层数据协议转换等-Ethernet
floating_multi
- Floating point multiplier
901_1
- 里面包含曼彻斯特编解码的大概描述及用Verilog编写的代码。-Which contains the Manchester encoding and decoding is probably described and written in Verilog code.
digital-clock
- 采用verilog语言将输出频率分频实现数字钟的基本功能：如时间显示，定点报时，整点报时，倒计时等。-Using verilog language to realize the basic function of digital clock by cut the output frequency , such as showing time, designated time,, countdown, etc.
VHDL-1
- 数字电路设计,好东西-数字电路设计,好东西-------------------
DAC7724_EP3C_1
- FPGA EP3C16F484C8N与DAC7724EP3C之间的通信程序-the code of communication between EP3C16F484C8N and DAC7724EP3C
mycpu
- VHDL cpu MUTIPYL ADD SUB JMP SHIFTL -VHDL cpu MUTIPYL ADD SUB JMP SHIFTL
VHDLProgrammingbyExample
- VHDL programming by example
UART(Verilog)
- Verilog 串口程序，可完成完整的数据接收与发送。代码注释清晰，程序易读。-Verilog UART
ads805
- 电设用到！用verilog编写的TI的ADS805的调试程序。测试平台是DE0 。-Electric facilities used! TI' s written in verilog ADS805 debugger. Test platform is DE0.
mimo_dectection20160112
- mimo检测算法的FPGA实现，包括最小迫零检测算法和ML检测算法，已在ISE上仿真通过-mimo detection algorithms on FPGA, including a minimum zero forcing detection algorithm and ML detection algorithm has been through in the ISE simulation