资源列表
traffic
- traffic light control by FPGA Quartos
Blockramhist
- 提供一个基于block RAM 的直方图统计，使用一个buffer解决了由于流水线产生的读写RAM时间差 主要提供设计思路，控制逻辑和输出可另行设计-block RAM hist
51cpldDesignSource
- fpga+c51的设计源码，精品收藏,整个互联网都没有几个这样的源码推荐下载-fpga+ c51 design source, Collections.The Internet are not recommended several such source code download
EEPROM
- verilog编写的EEPROM读写操作程序 有流水灯显示-EEPROM write verilog written operating procedures have water lights display
aurora_bram
- Xilinx SP605评估板 Aurora IP(GTP 简单协议) 核功能验证 调试源代码 chipscope验证通过-Xilinx SP605 Evaluation Kit Aurora IP core functional verification debugging source code and chipscope verified
K7DDR3
- 关于K7板子上ddr3的调试程序，用verilog语言写的-About debugger on K7 board ddr3, with the verilog language written
12345PS2
- ps2键盘接口VHDL程序，经过严格仿真，很有参考价值。-PS2 keyboard interface VHDL program, after a rigorous simulation, of great reference value.
HDB3
- hdb3键盘接口VHDL程序，经过严格仿真，很有参考价值。-HDB3 VHDL keyboard interface program, after a rigorous simulation, of great reference value.
proje2
- it is code for implement the FIFO in VHDL. FIFO is first in first out memory.
proje
- its ALU using VHDL. its parameter have 16 bits and doing logical and arithmetic functions
proje4
- It is 8 bit divisor. it is restoring algorithm implementation.
proje3
- it is ALU using VHDL language. it has inputs with 3 bits.