资源列表
GWPK2GWAK30
- GWPK2_GWAK30_30+_30Z示例，对于VHDL入门有一定帮助-GWPK2_GWAK30_30+ _30Z example, for a certain entry-VHDL help
New
- amba ahb master decoder
cpu
- 基于现场可编程(FPGA)技术和硬件描述语言-CPU design can be made
HardCamera
- The objective of this project is to create a driver for a camera module (we used the OV7620). After taking the image with the camera, the driver will store into the external asynchronous RAM, and then send it to the computer through a serial cable
RS232capture
- This approach, we feel, came very close to obtaining an image from the camera OV7620. Before we tried to capture a camera signal, we successfully transferred a test image from the FPGA s onboard RAM modules through RS232 to the PC program. This file
divide
- It is n-bit sequential divider in verilog language
ram
- ram的vhdl源代码在colloy实现-ram in the vhdl source code to achieve colloy
lab1
- lab1 report, with code -lab1 report, with codelab1 report, with code
sopcniosexample
- 通过quartusII的sopc构建一个简单的nios系统，里面还有简单nios实例，操作步骤很详细-Sopc through the quartusII to build a simple system nios, nios there is also a simple example of the steps in detail
seven_segment
- 用veirlog写成的七段显示器 可以把十进制转成七段显示器上面的显示数字-Paragraph written by veirlog display can display the metric system into the above paragraph shows that the number of
state_machine_design
- 这是讲解状态机的一个资料，里面讲解了摩尔和米勒状态机的设计实例，很详细且有实例。-This is a state machine on the information, which Moore and Miller explained the design of state machine instances, and there are examples of very detailed.
ad_conv
- 利用CPLD来控制AD进行电压采样，并将采样值输出-CPLD to control the use of AD to voltage sampling, and sampling the value of output