资源列表
voltage_measure
- 利用CPLD对输入信号测量幅度，保存数值-The use of CPLD measurement range of the input signal, save value
dig_scan
- 将AD采样的八位比特转化为十进制数值大小，并用数码管动态显示-The AD sample into the eight-bit decimal numerical size, and dynamic display with digital control
loopdisp
- 利用CPLD控制六个数码管动态显示所要显示的数值-CPLD to control the use of six LED dynamic display to display the numerical
VHDL
- 主要讲述了FPGA设计中的关键语言VHDL的学习-VHDL for FPGA study
dianziqin
- 基于FPGA实现八音电子琴的设计，并附带自动播放功能-The design of realization eight sound electronic organses, and supplementary auto broadcast function
led
- 此源码可以在EASYFPGA是实现跑马灯程序-led
uart_testbench
- opcore.org "uart16550" 项目的testbench-test bench of "uart16550" project
MAC_rd
- DM9000A读寄存器模块, verilog HDL-read DM9000A registers ， in verilog HDL
clk_div
- 一个时钟分频模块,in verilog hdl-clock division module in verilog hdl
VHDL
- VHDL的语言详解,很全,很好很强大 VHDL的语言详解,很全,很好很强大-VHDL
FPGA-baseddesignofdigitalrequencymeter
- 基于FPGA数字频率计的实现，文中有所有的源代码，仅供参考。-FPGA-based realization of the digital frequency meter, text in all the source code, for reference purposes only.
juzhenqufaqi
- 基于FPGA单精度浮点除法器的实现，有一些源代码，仅供参考。-FPGA-based single-precision floating-point divider realization, there are some source code, for reference purposes only.