资源列表
clock
- 用VHDL实现的完整数字钟代码，时分秒计时、校时、整点仿电台报时。-Used to achieve a complete VHDL code digital clock, accurate time at school, the whole point of imitation time radio.
VHDLwrkshp
- Workshop vhdl code from Esperan
CPU-Altera-FPGA
- 用CPU配置Altera公司的FPGA，简单明了，通俗易懂。-EASY TO USE
canbus
- verilog 和VHDL实现的can总线接口代码-the realization of verilog and VHDL code of the can bus interface
Quartus
- 1.七段数码管译码器 2.4人表决器 3.4进制加减法计数器~具有进位和借位功能-1. Seven-Segment LED Decoder 2.4 M 3.4 people voting machine counters ~ with addition and subtraction and by-bit binary function
Quartus32
- 1.8421码十进制计数器 2.分频系数为8，占空比为0.5的分频器 3.控制8个二极管的电路-Counter 2 decimal 1.8421 yards. Sub-frequency coefficient of 8, duty cycle of the divider 3 for the 0.5. 8 diode control circuit
Quartus4
- 1实现六个数码管串行扫描电路 2六个数码管滚动显示电路-1 to achieve the six digital control circuit 2, six serial digital scanning tube rolling display circuit
VHDL
- VHDL常用程序100例 实例丰富 基本上涵盖了常见的例子-VHDL example of 100 cases of common procedures covered basically the rich common example
verilog_soft
- verilog_soft学习资料 verilog_soft学习资料-verilog_soft learning materials learning materials verilog_soft learning materials verilog_soft
Verilog_tutorial
- Verilog_tutorial联系指导 Verilog_tutorial联系指导-Contact Verilog_tutorial contact Verilog_tutorial guidance guidance guidance Verilog_tutorial Contact
DE2_LCM_CCD
- DE2 CCD数码相机源代码，下载即可使用。方便学习。-DE2 CCD digital camera source code, you can use to download. Facilitate learning.
fifo_ptrs_gray
- fifo pointers in verilog gray code utilization for synchronius