资源列表
FPGA-while-practicing-learning
- FPGACPLD边练边学 快速入门VerilogVHDL》源程序-FPGACPLD while practicing learning- Quick Start VerilogVHDL source program
Deep-understanding-of-FPGA--design
- 深入理解Altera FPGA应用设计-Deep understanding of FPGA Altera application design
baskball
- fpga实现篮球定时器，可以两队交替得分，时间为24s-the basketball ，with time and code
div
- 简单的定时器程序，可以在很多地方用到，同时不会有逻辑错误。-Simple timer program that can be used in many places, but there will be no logic errors.
fifo
- 同步fifo，可以进行读写操作，使用rom ip核进行存储数据，可以作为参考。-Synchronous fifo, read and write operations can be performed using the rom ip core for storing data can be used as a reference.
display
- 数码管显示程序，支持6个数码管，包括译码和电平检测模块。-Digital tube display program, supports six digital control, including decoding and level detection module.
lab06
- 设计一4*4bit的寄存器文件 具备一组读端口及一组写端口 通过读端口可从0~3号的任意地址读取数据 通过写端口可向0~3号的任意地址写入数据 读写端口为“全双工”的工作方式 0~3号寄存器的复位值依次为“1、2、4、8” sw4~sw7为写数据端口 sw2~sw3为写地址；sw0~sw1为读地址；led0~led3用来显示读数据；写使能用按键实现；读使能可选 -Design of a 4* 4bit register file includes a read por
ISE
- 设计一4位比较器,画出门级电路图,用verilog语言完成设计。-Design a four comparators, drawing out level circuit diagram, complete the design using verilog language.
demo11
- 实现一个8bit计数器 复位时计数值为8‘hF0 复位后，计数器实现累加操作，步长为1，计数值达到8‘hFF后，从0开始继续计数 每0.5秒左右计数值加1 -Implementing a 8bit counter is reset when the count value 8' hF0 reset the counter for accumulator operation, in steps of 1, after the count reaches 8' hFF,
16FFT
- Xilinx的16点傅里叶分析，内有详细说明-The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary compone
1024FFT
- Xilinx的1024点傅里叶分析，内有详细说明-The xFFT1024 fast Fourier transform (FFT) Core computes a 1024-point complex FFT. The input data is a vector of 1024 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary
CRC
- 赛灵思的循环冗余校验（CRC），内服详细说明-The Cyclic Redundancy Check (CRC) is a checksum technique for testing data reliability and correctness. This application note shows how to implement Configurable CRC Modules with LocalLink interfaces. Users tailor the modul