资源列表
verilog_cordic_core
- A highly configurable 1st quadrant CORDIC core in verilog-Details Name: verilog_cordic_core Created: Sep 14, 2008 Updated: Aug 12, 2011 SVN Updated: Mar 10, 2009 SVN: Browse Latest version: download Statistics: View Other projec
EDK_adv212
- 控制ADV212 压缩的源代码 使用xilinx edk开发环境-adv 212 controller, using xilinx edk
LCD12864
- 该程序用于CPLD控制12864显示,显示内容见http://zhuxiangqing.blog.163.com/album/#m=2&aid=264724219&pid=8734321251-The program is used to control CPLD 12864，link:http://zhuxiangqing.blog.163.com/album/#m=2&aid=264724219&pid=8734321251 to view
lcd1602
- 该程序通过CPLD控制1602显示，显示效果见http://zhuxiangqing.blog.163.com/album/#m=2&aid=264724219&pid=8732102150-CPLD to control the program by 1602, the display see http://zhuxiangqing.blog.163.com/album/# m = 2 & aid = 264724219 & pid = 8732102150
axi_ad9361_tx_channel
- 采用硬件描述语言verilog进行AD9361芯片实现的代码-AD9361 using hardware descr iption languages Verilog code that chip
dds
- 采用硬件描述语言verilog进行DDS变换的实现的代码-Using hardware descr iption languages Verilog implementation of DDS converter code
hardware-qpskmodulate1
- 采用硬件描述语言verilog进行QPSK变换的实现的代码- Using hardware descr iption languages Verilog implementation of QPSK converter code
hardware-rake_mrc1
- 采用硬件描述语言verilog进行RAKE MRC变换的实现的代码-Using hardware descr iption languages Verilog implementation ofRAKE MRC converter code
FPGA
- FPGA调试的方法及常用工具 对初学者帮助很大-Methods and tools used to debug FPGA great help for beginners
fpga_DESIGN_examples
- 自己收集的常用的FPGA模块设计，大家分享啊 异步FIFO设计/伪随机序列应用设计/积分梳状滤波器(CIC)设计/伽罗华域GF（q）乘法器设计/除法器设计/常用加法器设计/常用乘法器设计/RS(204,188)译码器的设计/CORDIC数字计算机的设计-Common FPGA module design your own collection, to share ah Asynchronous FIFO design/application design pseudo-random s
DDS
- 用Verilog HDL 编写的一个最基本的DDS程序，发生正弦波-Verilog HDL prepared with a basic DDS program, the occurrence of a sine wave
dac
- dac interface sine wave and other waves