资源列表
REversible_tsgGate
- VHDL code for Reversible TSG gate and its application.
Adders-Using-VHDL
- VHDL code for Half adder, Full adder.
VHDL-Tutorial-in-Sequenctial-Circuits.-
- VHDL Codes for different sequential circuits. Includes Counter, State machines, Addders.
FPGA-I_LOOP
- 本程序是三角波产生程序，很实用，是进行PWM拨软件实现的关键软件之一-This procedure is a triangular wave generated procedures, it is practical, is one of the key software PWM to dial the software implementation
fifo
- 先进先出模块，该模块可以用来调节数据的速率，而且可以作为暂时存储器使用，一般的FPGA调试时使用较多。-frist in frist out
audioVHDL
- FPGA_Audio - project to implement and demonstrate audio on FPGA Using VHDL
VerilogHDL_PIC16c_Microcontroller
- VerilogHDLPIC16c - VerilogHDL implementation of PIC16c5x
8-bit-ALU-with-a-Newton-Raphson-Divider
- 8-bit ALU with a Newton-Raphson Divider Using Verilog
Formal-Verication-of--the-PCI-Local-Bus
- Formal Verication of the PCI Local Bus Using Verilog-Formal Verication of the PCI Local Bus Using Verilog
80211_Transmitter_VerilogHDL
- 802.11a Transmitter implementation Using Verilog
lab8
- matlab实现国歌播放实验,实验8，音乐播放器-matlab achieve national anthem playing experiment 8, music player
RS422_UART
- RS422 串口通讯 （包括 testbench，虚拟RAM，数据收发，波特率生成，数据接收抗干扰）-RS422 UART testbench BaudGen