资源列表
test2
- 此程序为汉字“正”的源程序，仅仅用于学习和交流使用，不当之处，望指正！-This program is the Chinese character " positive" the source, use only for learning and communication, inappropriate, hope correction!
main
- demux impelementation for vhdl muxing protocol
1
- 信号发生器VHDL实现,实现一种信号的产生-Signal generator VHDL implementation to achieve produce a signal
DE2_Default-source
- Altera FPGA DE2 Default Project File
core
- 串转并的电路转换器，并包含testbench。-The converter circuit about serial to parrel, including testbench.
DOT_LED
- 点亮LED，适用于FPGA 初学者，很不错的例子，简单、易懂-dot led
FPGA-VGA
- 基于FPGA VGA基本显示源码 晶振50M 分辨率 640 x 480-Based FPGA VGA basic source crystal display 640 x 480 resolution, 50M
SRTP2
- 基于FPGA利用verilog HDL编写的128bitAES加密算法电路-Verilog HDL-based FPGA use encryption algorithms written 128bitAES circuit
clock_retrive_lsy
- 用于E1接口数据时钟恢复，可提取相应的频率-Using for E1 interface, support 2M frequency recovery and retime
CPLD_EXample
- 非常适合新手学习CPLD的例程，从点亮流水灯，到VGA一步一步进阶。-CPLD is very suitable for novices to learn the routines, the lit water lights, step by step advanced to VGA.
project_wave_gen_code
- 设计并实现一个可产生正弦波、三角波和锯齿波的波形发生器。其工作频率为60MHz，可产生1MHz、2MHz、3MHz、4MHz、5MHz、6MHz、10MHz的正弦波、三角波和锯齿波。所产生波形的幅度、相位均可调整，输出数据的字长为12比特。应用环境为quartus 2-Design and implement a can produce sine, triangle, and sawtooth waveform generator. The operating frequency of 60MH
lcd
- 本代码利用verilog语言写的驱动LCD1602 其中LCD1602显示为英文。（LCD带字库）-This code is written in verilog use drive LCD1602 Which LCD1602 display in English. (LCD with font)